<?xml version="1.0" encoding="utf-8"?>
<rss version="2.0">
	<channel>
		<title>МоёМесто.ru :: igorgenius :: Verilog</title>
		<link>http://moemesto.ru/igorgenius/tags/Verilog</link>
		<description>Сервис интернет закладок МоёМесто.ru</description>
		<language>ru</language>
		<pubDate>Thu, 14 May 2026 04:36:42 +0300</pubDate>
		<image>
			<link>http://moemesto.ru/igorgenius/tags/Verilog</link>
			<url>http://moemesto.ru/icons/logo.jpg</url>
			<title>МоёМесто.ru</title>
		</image>
		<item>
			<title>Verilog.Net</title>
			<link>http://www.verilog.net/</link>
			<guid>http://moemesto.ru/link/538349</guid>
			<description>Free Verilog Tools</description>
			<pubDate>Sun, 01 Jun 2008 18:02:48 +0400</pubDate>
		</item>
		<item>
			<title>Model Checking @CMU</title>
			<link>http://www.cs.cmu.edu/~modelcheck/index.html</link>
			<guid>http://moemesto.ru/link/522138</guid>
			<description>Model checking is a method for formally verifying finite-state concurrent systems. Specifications about the system are expressed as temporal logic formulas, and efficient symbolic algorithms are used to traverse the model defined by the system and check if the specification holds or not. Extremely large state-spaces can often be traversed in minutes. The technique has been applied to several complex industrial systems such as the Futurebus+ and the PCI local bus protocols.</description>
			<pubDate>Tue, 27 May 2008 07:37:37 +0400</pubDate>
		</item>
		<item>
			<title>Verilog Page</title>
			<link>http://www.asic-world.com/verilog/</link>
			<guid>http://moemesto.ru/link/513220</guid>
			<description>Страница посвящена языку описания аппаратуры Verilog HDL. Даны практические советы по использованию языка, примеры на Verilog, обзор инструментов и полезные ссылки на ресурсы по Verilog</description>
			<pubDate>Fri, 23 May 2008 12:40:40 +0400</pubDate>
		</item>
  </channel>
</rss>
